Open-Source Hardware

Cryptography and Computer-Network Security



Open Source Hardware Cores

Secret-key Ciphers

No. Title / URL Description Language License
1 AES 128 Encryption/Decryption A 128-bit hardware implementation of AES (senior project, Bradley University) VHDL


2 AES (Rijndael) IP Core AES IP core Verilog


3 128/192 AES A 128 bits and a 192 bits key length AES coprocessor focusing on very low area applications Verilog/System C LGPL
4 AES128 Yet another implementation of AES VHDL LGPL
6 NSA AES VHDL Models AES (Rijndael) implementation VHDL Open
7 Blowfish VHDL Core
Blowfish encryption algorithm in synthesizable VHDL VHDL GPL
8 DES Core
Simple DES implementation in VHDL VHDL GPL
9 Basic DES Crypto Core BasicDES Cryptography Core is a small, fast implementation of the DES-56 encryption standard VHDL LGPL
10 3DES (Triple DES) / DES (VHDL) VHDL implementation of Triple-DES (pipelined) and DES cryptographic algorithms VHDL LGPL
11 DES/Triple DES IP Cores DES/Triple-DES core Verilog LGPL
12 SystemC/Verilog DES (2) SystemC DES is a implementation of the DES algorithm in SystemC focusing on low area applications Verilog/System C LGPL
13 NSA VHDL Models Serpent implementations VHDL Open
14 NSA VHDL Models Twofish implementation VHDL Open
15 Twofish 128/192/256 (1) VHDL implementation of the Twofish cipher for 128,192 and 256 bit keys VHDL GPL
16 XTEA Crypto Core An implementation of the XTEA block cipher Verilog LGPL

Public-key Ciphers


No. Title / URL Description


Basic RSA Encryption Engine Simple implementation of the RSA Public Key Encryption algorithm VHDL LGPL

Cryptographic Hash Functions

No. Title / URL Description Language License
1 SystemC/Verilog MD5 A MD5 hash algorithm implementation in SystemC, including the equivalent synthesizable Verilog translation Verilog/System C LGPL
2 Pancham Pancham is a IP core that implements the MD5 message digest algorithm. Verilog/System C LGPL
3 SHA cores A collection of SHA (Secure Hash Algorithm) cores Verilog LGPL